This application relies from priority upon Korean Patent Application No. 1999-37153, filed on Sep. 2, 1999, the contents of which are herein incorporated by reference in their entirety.
The present invention is related to a random access memory device, and specifically to an address generating and decoding circuit realized to a burst-type and high-speed random access memory device, which has a single data rate and double data rate scheme.
Video RAM (random access memory), synchronous RAM and burst RAM each require a sequence of internally generated addresses (referred to as xe2x80x9can address burstxe2x80x9d, xe2x80x9can address sequencexe2x80x9d or xe2x80x9ca serial addressxe2x80x9d) to support a high-speed data access operation. Typically the start address of a particular address burst is provided from an external source (e.g. a host computer or a processor), and as subsequent clock signals arrive at the address generator, the following addresses in the burst are sequentially generated for the duration of the burst.
Techniques associated with the address generator for performing such a function are disclosed in U.S. Pat. Nos. 5,596,616, 5,708,688, and 5,452,261. These patents utilize a single data rate (SDR) scheme, in which a data element is inputted/outputted to/from a burst-type RAM during a cycle of a system clock. As the above-described burst mode is provided to a random access memory, a data access operation of the memory is possible. Nevertheless, a user requires gradually requires more rapid data access operation.
Among techniques for speeding up the data access operation, one is a double data rate (DDR) scheme, in which at least two data are inputted/outputted to/from a memory device during one cycle of a system clock. An operation speed (or performance) of the RAM incorporating the DDR scheme is thus doubled to one using the SDR scheme. In order to input/output two data elements during one cycle of the system clock, addresses are required in a first logic state (e.g., a low level) period of the system clock, and in a second logic state (e.g., a high level) period thereof, respectively. Therefore, unlike the from address generators of the above-mentioned patents only used at the SDR mode, a new address generator is required which is capable of being used at both the SDR mode and the DDR mode.
It is therefore an object of the invention to provide an address generating and decoding circuit suitable for a burst-type random access memory device supporting both a single data rate mode and a double data rate mode.
This and other objects, advantages and features of the present invention are provided by the invention. An address generating and decoding circuit for use in a burst-type random access memory device has a single data rate (SDR) mode, in which only one data clement is inputted/outputted in/from the memory device during a system clock cycle, and a double data rate (DDR) mode, in which two data elements are inputted/outputted in/from during the system clock cycle.
The address generating and decoding circuit of the invention comprises an address generator for producing a sequence of burst addresses. It produces them in response to an initial address which is a part of an externally applied address, a first control signal indicative of a burst type, and a second control signal indicative of either the DDR mode or the SDR mode. The first burst addresses of the sequence are synchronized with first and second clock signals. The circuit also includes decoding means for sequentially receiving the burst addresses to decode a first burst address thus received and the remaining address of the externally applied address.